This application claims the priority benefit of Taiwan application serial no. 89126183, filed Dec. 8, 2000.
1. Field of Invention
The present invention relates generally to a method and apparatus of a digital echo canceller. More particularly, the present invention relates to a method and apparatus of a digital echo canceller that only responds to echo signals to perform a multiplication-and-addition function.
2. Description of the Related Art
FIG. 1 illustrates a performance of a full-duplex digital transceiver. Both ends of the full-duplex digital transceiver are connected to a cable 22. Each end of the full-duplex digital transceiver has a transceiver 18 or 20. The transceiver 18 at the left end of the full-duplex digital transceiver comprises a transmitter (TX) 12, a receiver (RX) 14 and a hybrid circuit 16. The transmitter 12 and the receiver 14 are connected to the hybrid circuit 16 to perform receiving and transmitting signals.
If the transceiver 18 at the left end of the full-duplex digital transceiver is used as a near-end transceiver, the other transceiver at the right end will be a far-end transceiver. When the transmitter 12 transmits a signal to the far-end of the full-duplex digital transceiver 20, the transmitter will often not match the impedance of the far-end full-duplex digital transceiver 20 due to a transmitting cable 22. A far-end echo signal that will transmit to the near-end of the full-duplex digital transceiver 16 influences the received signal of the receiver 14. An interfering noise will occur.
To prevent the above-mentioned state from occurring, the conventional method will require designing a canceller to eliminate the echo signals. The structure illustrated in FIG. 2 of an adaptive finite impulse response digital echo canceller (adaptive FIR digital echo canceller). Xn signals are transmitted to a plurality of delay circuits D. Xn signals with an output of each delay circuit D to produce signals. These signals are multiplied respectively to a plurality of the significant coefficients C0, C1, C2, . . . CNxe2x88x922, CNxe2x88x921 to produce multiplied values. These values of the multiplication are then added together to produce a sum (the sum xcexa3 is shown on the FIG. 2). An estimated echo signal is thus produced to eliminate the interference noise.
The above mentioned structure transmits signals utilizing a longer transmitting cable and a higher frequency (for example, a gigabit ethernet case, at the sample rate of 125 Mhz) to produce an echo signal""s length that is shown on FIG. 3 is approximately 80 EC taps long. When the length of the echo signal is longer, the number of the significant coefficients C0, C1 . . . CNxe2x88x922, CNxe2x88x921 are required to multiply respectively to the signals that are transmitted by the delay circuits D of FIG. 2 will increase. As a result the amount of addition and multiplication operations that have to be calculated will also increase. The whole operation is not only complex, but the cost of the hardware is also high.
According to above, the present invention provides an installation of a digital echo canceller and method therefor. It is an object of the present invention to operate a multiplication-and-addition according to an echo part that relates to an echo signal so that an unnecessary circuit design can be omitted.
The present invention provides an apparatus of a digital echo canceller. The digital echo canceller is suitable for a full-duplex digital transceiver to eliminate an echo signal that is produced by the full-duplex digital transceiver.
The receiver of the full-duplex digital transceiver is connected to a first receiving end and a second receiving end by a cable. From the first receiving end to produce an input signal.
The structure of the present invention comprises a plurality of first-set delay circuits, a selector, a plurality of second-set delay circuits, a plurality of multipliers and an adder. The plurality of first-set delay circuits comprise an input and an output, wherein the input and the output are connected in series. The first input received signals. The selector comprises an input and an output. The input is according to a length of a cable to select which part of the output of the first-set delay circuit to connect. The plurality of second-set delay circuit comprise a input and output, wherein the input and the output Are connected in series. The first input is connected to the output of the selector. The number of the plurality of the multipliers is the same as the second-set of the delay circuits. The multipliers are connected respectively to each output of the second-set delay circuits. Each of these multipliers multiplies respectively to an EC coefficient to produce signals. An addisor will receive all these signals that are produced from the multipliers and add these values together to produce a sum, wherein the sum is an estimated echo signal that will cancel the echo signal.
An echo number of an insignificant part that is produced by the echo signal depends on the length of a cable. The connecting operation of the selector""s input is according to the response values of the insignificant part to decide which output of the first-set delay circuits shall be connected to.
An equation that calculates the length of a cable is Pr=∫Hc2(ƒ)P(ƒ)dƒ. Where P(f) is a frequency response of TX signal that is an input signal produced by one of the receiving end of the full-duplex digital transceiver; Hc(ƒ) is a frequency response of cable channel and Pr is a received signal power that is produced from the other receiving end. From the equation, the cable length is directly related to Hc(ƒ) and P(f). The values of Hc(ƒ) and P(f) can be obtained from a table. We can then approximately estimate the cable length. We normally design the quantity of the second-set delay circuits the same as the response values of the significant part of the echo signal, for example, 20.
A designed selector is to estimate the length of a cable. The selector is according to the input signal and the received signal to decide the response values of the insignificant part of the echo signal. Multiplication and addition will carry out only at the response region of the significant part of the echo signal to produce an estimated echo signal. The estimated echo signal is to cancel the echo. This process can avoid unnecessary operation in order to reduce the cost of the hardware.
The present invention provides a method of a digital echo canceller which is suitable for a system of a full-duplex digital transceiver to produce a signal, wherein the signal is to cancel an echo signal. A cable is connected to a first receiving end and a second receiving end, the steps comprise: producing an input signal from the first receiving end; measuring a received signal from the second receiving end after transmission. The cable length is estimated according to the received signal and the input signal. The length of the cable decides a response value of an insignificant part of the echo signal. Values of a significant part of the echo signal are multiplied respectively to a plurality of significant coefficients. All the values after the multiplication are added together to produce an estimated echo signal. The estimated echo signal is to cancel the echo signal.
In the above-mentioned embodiment, the relationship of the received signal power Pr that is directly related to the frequency response of TX signal P(f) and the frequency response of the cable channel Hc(ƒ), wherein Pr=Hc2(ƒ)P(ƒ)dƒ. The values of the Hc(f) and P(f) can be obtained from a table, and because the cable length is directly related to Hc(ƒ) and P(f) therefore the cable length can be approximately estimated from the equation.